This invention relates to transfer of data between an integrated circuit device and a test access port for testing purposes.
Complex integrated circuit devices often include a boundary scan architecture to aid in testing and debugging the device. The boundary scan architecture incorporates a chain of registers coupled to input (I/O) pins on the device. A standard interface, known as the Joint Test Action Group (JTAG) interface, specifies a particular test access port for interfacing with the scan architecture. The JTAG test access port, sometimes referred to as the “TAP,” facilitates external access to integrated circuit devices. The JTAG interface is defined by IEEE Standard 1149.1 (IEEE Std. 1149.1-1990, published 1990, and entitled “Test Access Port and Boundary-Scan Architecture”).
With the JTAG interface, a debug controller can be used to issue boundary scan commands to the test access port for shifting the scan chains into the integrated circuit, thereby initializing the integrated circuit to a known state. In addition, the debug controller may shift data from the scan chains, and provide the data to the test access port. In this manner, application developers can verify proper operation of code developed for the integrated circuit device.